Course by: Dr Alizadeh

This repository contains five Digital Logic Design projects implemented in SystemVerilog and simulated using Modelsim simulator. Projects cover combinational and sequential circuits, ALU design, pseudo-random number generation, and division units.

Projects

  1. SystemVerilog Introduction & Simulation

    • Learn SystemVerilog syntax and simulation workflow.
    • Create simple combinational modules.

  2. ALU Design (Combinational Modules)

    • Implement arithmetic (add, subtract) and logic (AND, OR, XOR) operations.
    • Modular design for easy reuse and simulation verification.

  3. Pseudo-Random Number Generator

    • Design hardware for generating pseudo-random numbers using LFSR or similar methods.
    • Test randomness through simulation.

  4. Sequential Circuits

    • Design counters, shift registers, and finite state machines.
    • Verify timing and functionality with simulation.

  5. Divider Unit

    • Implement integer division with quotient and remainder.
    • Can be sequential or combinational.

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